Competitive yield learning requires defect characterization and rapid resolution of systematic and random defect issues during early development of semiconductor devices. For example, E-beam inspection tools provide high sensitivity assessment as well as the ability to localize defects for cross-sectioning. Hence, test structures have been used with E-beam inspection tools to characterize known systematic defect issues occurring in integrated circuits, such as contact-to-gate shorts, worm hole leakage paths, contact printing issues, and sparse hole processing.
E-beam testing has also been used for inspection of random defects such as dislocations and other localized current leakage paths on product wafers, and has provided a means of quantifying dislocation and/or other defect densities with a short cycle time. Traditionally, dislocation inspections have been done using static random access memory (SRAM) structures. However, as process improvements are made, the SRAM cells become less sensitive indicators of the tendency to form dislocations. Furthermore, several types of defects cannot typically be detected using conventional E-beam techniques because of their location in the circuit. For example, dislocations and “pipes” (dislocations containing metal) occurring under gate electrodes and field dielectric regions typically go undetected using conventional E-beam testing. In general, such features typically result in leakage currents at level insufficient to result in a distinguishable contrast signal during a typical E-beam scan. Therefore, what is needed is a set of test structures for use with both E-beam and other defect detection techniques to allow detection and identification of dislocations, pipes, and other types of defects when conventional E-beam inspection techniques are ineffective.